Semiconductor integrated circuit and operating method thereof

ABSTRACT

A semiconductor integrated circuit and its operating method are provided. The present circuit has first and second supply terminals capable of supplying first and second power supply voltages respectively, an input voltage selection circuit coupled to the first and second supply terminals, and first and second power supply switches. The input voltage selection circuit includes a power-on reset circuit, an input voltage detection circuit and a control circuit. When the supply of the first or second power supply voltage to one of both supply terminals is detected upon completion of a power on reset operation, one of both power supply switches and the other thereof are controlled to on and off respectively. When the supply of both power supply voltages to both supply terminals is detected, the one thereof and the other thereof are respectively controlled to on and off according to the preset order of precedence.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2012-120696 filed onMay 28, 2012 including the specification, drawings and abstract isincorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to a semiconductor integrated circuit andan operating method thereof and particularly to a technology effectivein implementing an electronic circuit for automatically selecting apower supply to be used out of a plurality of power supplies.

As has been described in, for example, each of the following PatentDocuments 1 and 2, an IC card is equipped with a semiconductorintegrated circuit and an antenna coil, and the supply of power to theIC card is performed by receiving an RF signal outputted from areading/writing device called a card reader/card writer by the antennacoil and rectifying the same by a rectifier circuit. Thus, the IC cardhaving no power supply on its card side is becoming pervasive in anautomatic ticket system, e-cash, logistics management, etc. Thus, sincethe IC card is RF-power supplied and on the other hand, uniqueidentification information (ID information) has been stored in abuilt-in non-volatile memory, it is called an RFID card.

On the other hand, a wireless power delivery system has been inwidespread use which is called “just-to-place charging” in which aportable device such as a smart phone is simply placed in a dedicatedcharging table without coupling the portable device to a power supplycable to thereby enable the charging of the portable device. This typeof wireless power delivery system intends to cope with the fact that thebattery drain of the cellular phone called “smart phone” is large. Thatis, the smart phone is a multifunction cellular phone having a highaffinity to Internet and based on the functions of a personal computer,or a multifunction cellular phone with a PDA function added to aphone/mail, which may be abbreviated as “smapho” or “smaho”. Thewireless power delivery system is based on the international standardcalled Qi (chi) established by Wireless Power Consortium (WPC) of theindustry group. Both of a transmission side device and a reception sidedevice are respectively provided with coils to thereby enable the supplyof power from the transmission side device to the reception side deviceby an electromagnetic induction system. The advantages of the wirelesspower delivery system are that there is no need to plug or unplug apower connector for charging and the operation of opening and closing aconnector cover for a power connector of a portable device in particularcan be omitted.

Further, it has been described in the following Patent Document 3 thatin an electronic device selectively coupled to two or more types ofpower supplies to charge a battery, a controller is used to couple theelectronic device to another power supply soon when the coupling to thepower supply subjected to the supply of power is released, to therebystart the charging of the battery. That is, the control provided by thecontroller resides in that the battery is charged by an AC power supplywhile current is being supplied from the AC power supply to an ACcoupling part, whereas while current is being supplied from an externaldevice to an external device coupling part without the supply of currentfrom the AC power supply to the AC coupling part, the battery is chargedby the power supply of the external device. When the external devicecoupling part is coupled to the external device while the battery isbeing charged by the AC power supply, the controller particularlyperforms an initial communication with the external device to therebyconduct charge settings necessary to charge the battery through theexternal device. Specifically, the external device coupling part is aUSB coupling part, and an interface of another standard such as IEEE1394or the like can also be adopted. Since the current from the AC powersupply is larger than that from the external device when the electronicdevice is coupled to both of the AC power supply and the externaldevice, the controller serves to charge the battery through the AC powersupply.

RELATED ART DOCUMENTS Patent Document [Patent Document 1] JapaneseUnexamined Patent Publication Laid-Open No. 2009-4949 [Patent Document2] Japanese Unexamined Patent Publication Laid-Open No. 2010-9353[Patent Document 3] Japanese Unexamined Patent Publication Laid-Open No.2011-155830 SUMMARY

Prior to the present invention, the present inventors have been involvedin the development of a semiconductor integrated circuit for batterycharging control, which is capable of operation by a plurality of powersupply voltages of an AC-DC power supply voltage generated byrectification/smoothing of an AC power supply voltage from an AC powersupply, a USB power supply voltage from USB coupling, and a power supplyvoltage based on a wireless power delivery of the above wireless powerdelivery system.

In the process of its development, the present inventors have discussedthe method of charging the battery by the power supplies described inthe Patent Document 3. According to the discussion made by the presentinventors, however, there has been revealed a problem that animplementation method for automatically selecting a used power supply inaccordance with the presence or absence of the supply of a plurality ofpower supplies has not been described in the Patent Document 3. That is,the semiconductor integrated circuit for the battery charging control,which is capable of operation by the power supply voltages describedabove, needs to implement an electronic circuit that automaticallyselects a power supply to be used from a plurality of power supplies.

While means and the like for solving such a problem are described below,other objects and novel features of the present invention will becomeapparent from the description of the present specification and theaccompanying drawings.

A summary of a representative embodiment disclosed in the presentapplication will be explained in brief as follows:

A semiconductor integrated circuit (212) according to a typicalembodiment is equipped with a first supply terminal (T1) capable ofsupplying a first power supply voltage, a second supply terminal (T2)capable of supplying a second power supply voltage, an input voltageselection circuit (2124), a first power supply switch (SW1, SW2) and asecond power supply switch (SW3) (refer to FIG. 2).

The input voltage selection circuit (2124) includes a power-on resetcircuit (21244), an input voltage detection circuit (21248) and acontrol circuit (21245, 21246) (refer to FIG. 4).

When the supply of the first or second power supply voltage to eitherthe first or second supply terminal is detected by the input voltagedetection circuit at the end of a power on reset operation of thepower-on reset circuit, one of the first and second power supplyswitches and the other thereof are respectively controlled to an onstate and an off state by the control circuit that has responded to itsdetection.

When the supply of both of the first and second power supply voltages toboth of the first and second supply terminals is detected by the inputvoltage detection circuit at the end of the power on reset operation ofthe power-on reset circuit, one of the first and second power supplyswitches and the other thereof are respectively controlled to an onstate and an off state by the control circuit in accordance with theorder of precedence set in advance.

An advantageous effect obtained by a typical one of embodimentsdisclosed in the present application will be explained in brief asfollows:

According to the present semiconductor integrated circuit (212), anelectronic circuit for automatically selecting a power supply to be usedout of a plurality of power supplies can be implemented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing a configuration of a multifunction cellularphone equipped with a semiconductor integrated circuit 212 for batterycharging control, according to a first embodiment;

FIG. 2 is a diagram illustrating a configuration of the semiconductorintegrated circuit 212 for the battery charging control, according tothe first embodiment shown in FIG. 1;

FIG. 3 is a diagram depicting functions of external terminals of thesemiconductor integrated circuit 212 for the battery charging control,according to the first embodiment shown in FIG. 2;

FIG. 4 is a diagram showing a configuration of an input voltagedetection circuit 2124 for the selection of an operation mode atstart-up of the semiconductor integrated circuit 212 according to thefirst embodiment shown in FIG. 2;

FIG. 5 is a diagram illustrating the operation of automaticallyselecting a power supply to be used out of a plurality of power suppliesby the semiconductor integrated circuit 212 according to the firstembodiment shown in FIGS. 2 and 4;

FIG. 6 is a diagram depicting the operation of automatically selecting apower supply to be used out of a plurality of power supplies by thesemiconductor integrated circuit 212 according to a second embodimentshown in FIGS. 2 and 4;

FIG. 7 is a diagram showing waveforms of respective parts of thesemiconductor integrated circuit 212 according to the second embodimentshown in FIGS. 2 and 4 at Steps S506, S507, S602 and S603 during theoperation of automatically selecting the power supply to be used out ofthe power supplies according to the second embodiment shown in FIG. 6;and

FIG. 8 is a diagram illustrating the operation of automaticallyselecting a power supply to be used out of a plurality of power suppliesby the semiconductor integrated circuit 212 according to a thirdembodiment shown in FIGS. 2 and 4.

DETAILED DESCRIPTION 1. Summary of the Embodiments

A summary of typical embodiments of the invention disclosed in thepresent application will first be explained. Reference numerals of theaccompanying drawings referred to with parentheses in the description ofthe summary of the typical embodiments only illustrate elements includedin the concept of components to which the reference numerals are given.

[1] A semiconductor integrated circuit (212) according to a typicalembodiment is equipped with a first supply terminal (T1) capable ofsupplying a first power supply voltage, a second supply terminal (T2)capable of supplying a second power supply voltage, an input voltageselection circuit (2124) coupled to the first supply terminal and thesecond supply terminal, a first power supply switch (SW1, SW2) and asecond power supply switch (SW3) (refer to FIG. 2).

The input voltage selection circuit (2124) includes a power-on resetcircuit (21244), an input voltage detection circuit (21248) and acontrol circuit (21245, 21246) (refer to FIG. 4).

In response to the supply of the first power supply voltage to the firstsupply terminal (T1) and the supply of the second power supply voltageto the second supply terminal (T2), the power-on reset circuit (21244)generates a power on reset signal (POR).

The input voltage detection circuit (21248) generates a first voltagedetection output signal (Vdet1) in response to the supply of the firstpower supply voltage to the first supply terminal (T1). The inputvoltage detection circuit (21248) generates a second voltage detectionoutput signal (Vdet2) in response to the supply of the second powersupply voltage to the second supply terminal (T2).

The control circuit (21245, 21246) controls the first power supplyswitch and the second power supply switch in response to the power onreset signal (POR), the first voltage detection output signal (Vdet1)and the second voltage detection output signal (Vdet2).

The input voltage detection circuit (21248) detects the supply of thefirst power supply voltage to the first supply terminal (T1) and thesupply of the second power supply voltage to the second supply terminal(T2) at a timing of a change in the level of the power on reset signal(POR) responsive to the end of a power on reset operation of thepower-on reset circuit (21244).

In a first case where at the timing of the change in the level of thepower on reset signal, the input voltage detection circuit detects thesupply of the first power supply voltage to the first supply terminalbut does not detect the supply of the second power supply voltage to thesecond supply terminal, the control circuit controls the first powersupply switch and the second power supply switch to an on state and anoff state respectively after the end of the power on reset operation(FIGS. 5: S504 and S505).

The first power supply switch and the second power supply switch arerespectively controlled to the on state and the off state respectivelyafter the end of the power on reset operation, whereby the first powersupply switch controlled to the on state supplies the first power supplyvoltage supplied to the first supply terminal to a load (3, 26) (FIG. 5:S505).

In a second case where at the timing of the change in the level of thepower on reset signal, the input voltage detection circuit detects thesupply of the second power supply voltage to the second supply terminalbut does not detect the supply of the first power supply voltage to thefirst supply terminal, the control circuit controls the first powersupply switch and the second power supply switch to an off state and anon state respectively after the end of the power on reset operation(FIG. 5: S506 and S507).

The first power supply switch and the second power supply switch arerespectively controlled to the off state and the on state respectivelyafter the end of the power on reset operation, whereby the second powersupply switch controlled to the on state supplies the second powersupply voltage supplied to the second supply terminal to the load (3,26) (FIG. 5: S507).

In a third case where at the timing of the change in the level of thepower on reset signal, the input voltage detection circuit detects thesupply of the first power supply voltage to the first supply terminaland the supply of the second power supply voltage to the second supplyterminal, the control circuit controls one of the first power supplyswitch and the second power supply switch and the other thereof to an onstate and an off state respectively after the end of the power on resetoperation (FIG. 5: S508 and S509).

In the third case, the one of the first power supply switch and thesecond power supply switch and the other thereof are respectivelycontrolled to the on state and the off state in accordance with theorder of precedence set to the control circuit in advance.

The one thereof controlled to the on state supplies the first powersupply voltage or the second power supply voltage supplied to the firstsupply terminal or the second supply terminal to the load (3, 26) (FIG.5: S505).

According to the embodiment, an electronic circuit for automaticallyselecting a power supply to be used out of a plurality of power suppliescan be implemented.

A semiconductor integrated circuit (212) according to a preferredembodiment further includes a first external output terminal (T4) and asecond external output terminal (T3) which supply the first power supplyvoltage or the second power supply voltage to a first external load (3)and a second external load (26) each taken as the load.

The semiconductor integrated circuit (212) furthermore includes anoutput P channel MOS transistor (Mp0) coupled between the first externaloutput terminal and the second external output terminal.

When either of the first power supply switch and the second power supplyswitch is controlled to an on state after the end of the power on resetoperation, the output P channel MOS transistor (Mp0) is controlled to anon state by the control circuit (21245, 21246).

The control of the output P channel MOS transistor to the on stateenables the first power supply voltage or the second power supplyvoltage to be supplied to the second external load through the output Pchannel MOS transistor and the second external output terminal (T3)(refer to FIGS. 2 and 4).

In another preferred embodiment, the first external output terminal (T4)is configured so as to be capable of supplying the first power supplyvoltage or the second power supply voltage to the first external load(3) corresponding to another semiconductor integrated circuit taken asan active device.

The output P channel MOS transistor and the second external outputterminal are configured so as to be capable of supplying the first powersupply voltage or the second power supply voltage to the second externalload (26) taken as a battery (refer to FIG. 2).

In a further preferred embodiment, the input voltage selection circuit(2124) further includes an input voltage selection switch (21242) and agate drive circuit (21249).

The input voltage selection switch includes a first input P channel MOStransistor (Mp1) and a second input P channel MOS transistor (Mp2). Asource of the first input P channel MOS transistor is coupled to thefirst supply terminal. A source of the second input P channel MOStransistor is coupled to the second supply terminal.

During a power on reset period of the power-on reset circuit (21244),the gate drive circuit (21249) controls both of the first and secondinput P channel MOS transistors of the input voltage selection switch toan on state.

During the power on reset period, an operating voltage (Vcc) to besupplied to the power-on reset circuit is generated from a drain of thefirst input P channel MOS transistor or a drain of the second input Pchannel MOS transistor (refer to FIG. 4).

In yet another preferred embodiment, in the first case, the gate drivecircuit controls the first and second input P channel MOS transistors ofthe input voltage selection switch to an on state and an off staterespectively.

In the second case, the gate drive circuit controls the first and secondinput P channel MOS transistors of the input voltage selection switch toan on state and an off state respectively.

In the third case, the gate drive circuit controls one of the first andsecond input P channel MOS transistors of the input voltage selectionswitch and the other thereof to an on state and an off staterespectively in accordance with the order of precedence set to thecontrol circuit in advance (refer to FIG. 4).

In a still further preferred embodiment, the input voltage selectioncircuit (2124) further includes a voltage comparison/selection circuit(21243) having a first input terminal (Node1), a second input terminal(Nodet2) and an output terminal.

The first input terminal (Node1) of the voltage comparison/selectioncircuit is coupled to the drain of the first input P channel MOStransistor of the input voltage selection switch.

The second input terminal (Node2) of the voltage comparison/selectioncircuit is coupled to the drain of the second input P channel MOStransistor of the input voltage selection switch.

The operating voltage supplied to the power-on reset circuit isgenerated from the output terminal of the voltage comparison/selectioncircuit.

The voltage comparison/selection circuit compares a voltage of the firstinput terminal and a voltage of the second input terminal to select ahigh voltage and thereby outputs the high voltage as the operatingvoltage supplied from the output terminal to the power-on reset circuit(refer to FIG. 4).

In a still further embodiment, with the occurrence of the first case, afourth case in which the input voltage detection circuit (2124) detectsthe supply of the second power supply voltage to the second supplyterminal occurs after the first and second power supply switches arerespectively controlled to the on state and the off state (FIG. 6: S505)after the end of the power on reset operation (FIG. 6: S600).

In response to the occurrence of the fourth case, the control circuitcontrols the one of the first power supply switch and the second powersupply switch and the other thereof to the on state and the off staterespectively in accordance with the order of precedence set to thecontrol circuit in advance, as with the third case.

With the occurrence of the second case, a fifth case in which the inputvoltage detection circuit (2124) detects the supply of the first powersupply voltage to the first supply terminal occurs after the first andsecond power supply switches are respectively controlled to the offstate and the on state (FIG. 6: S507) after the end of the power onreset operation (FIG. 6: S602).

In response to the occurrence of the fifth case, the control circuitcontrols the one of the first power supply switch and the second powersupply switch and the other thereof to the on state and the off staterespectively in accordance with the order of precedence set to thecontrol circuit in advance, as with the third case (FIG. 6: S603).

With the occurrence of the third case, a sixth case in which the inputvoltage detection circuit (2124) detects the supply of the second powersupply voltage to the second supply terminal occurs after the one of thefirst and second power supply switches and the other thereof arerespectively controlled to the on state and the off state (FIG. 6: S509)after the end of the power on reset operation (FIG. 6: S604).

In response to the occurrence of the sixth case, the control circuitcontrols the one of the first power supply switch and the second powersupply switch and the other thereof to the on state and the off staterespectively in accordance with the order of precedence set to thecontrol circuit in advance, as with the third case (FIG. 6: S605).

In a still further preferred embodiment, with the occurrence of thefirst case, a fourth case in which the input voltage detection circuit(2124) detects the supply of the second power supply voltage to thesecond supply terminal occurs after the first and second power supplyswitches are respectively controlled to the on state and the off state(FIG. 8: S505) after the end of the power on reset operation (FIG. 8:S600).

In response to the occurrence of the fourth case, the semiconductorintegrated circuit is capable of notifying the occurrence of the fourthcase to another semiconductor integrated circuit described above takenas the first external load (FIG. 8: S800).

In response to a first notice indicative of the occurrence of the fourthcase, the control circuit controls the first power supply switch and thesecond power supply switch in accordance with a first indicationsupplied from another semiconductor integrated circuit described aboveto the semiconductor integrated circuit (FIG. 8: S801-S802).

In accordance with the first indication, the control circuit controlsthe first power supply switch and the second power supply switch to anon state and an off state respectively (FIG. 8: S505) or controls thefirst power supply switch and the second power supply switch to an offstate and an on state respectively (FIG. 8: S802).

With the occurrence of the second case, a fifth case in which the inputvoltage detection circuit (2124) detects the supply of the first powersupply voltage to the first supply terminal occurs after the first andsecond power supply switches are respectively controlled to the offstate and the on state (FIG. 8: S507) after the end of the power onreset operation (FIG. 8: S602).

In response to the occurrence of the fifth case, the semiconductorintegrated circuit is capable of notifying the occurrence of the fifthcase to another semiconductor integrated circuit described above takenas the first external load (FIG. 8: S803).

In response to a second notice indicative of the occurrence of the fifthcase, the control circuit controls the first power supply switch and thesecond power supply switch in accordance with a second indicationsupplied from another semiconductor integrated circuit described aboveto the semiconductor integrated circuit (FIGS. 8: S804-S805).

In accordance with the second indication, the control circuit controlsthe first power supply switch and the second power supply switch to anoff state and an on state respectively (FIG. 8: S507) or controls thefirst power supply switch and the second power supply switch to an onstate and an off state respectively (FIG. 8: S805).

With the occurrence of the third case, a sixth case in which the inputvoltage detection circuit (2124) detects the supply of the second powersupply voltage to the second supply terminal occurs after the one of thefirst and second power supply switches and the other thereof arerespectively controlled to the on state and the off state (FIG. 8: S509)after the end of the power on reset operation (FIG. 8: S604).

In response to the occurrence of the sixth case, the semiconductorintegrated circuit is capable of notifying the occurrence of the sixthcase to another semiconductor integrated circuit described above takenas the first external load (FIG. 8: S806).

In response to a third notice indicative of the occurrence of the sixthcase, the control circuit controls the first power supply switch and thesecond power supply switch in accordance with a third indicationsupplied from another semiconductor integrated circuit described aboveto the semiconductor integrated circuit (FIGS. 8: S807-S808).

In accordance with the third indication, the control circuit controlsthe first power supply switch and the second power supply switch to anon state and an off state respectively (FIG. 8: S509) or controls thefirst power supply switch and the second power supply switch to an offstate and an on state respectively (FIG. 8: S808).

A semiconductor integrated circuit (212) according to a specificembodiment further includes a step-down DC-DC converter (2121) and alinear regulator (2122) coupled in parallel between the first supplyterminal (T1) and the first power supply switch (SW1, SW2).

The linear regulator operates as a series regulator which quicklyoperates immediately after power-on based on the supply of the firstpower supply voltage to the first supply terminal.

The step-down DC-DC converter (2121) operates as a switching regulatorhaving power efficiency higher than the linear regulator (refer to FIG.2).

As the most specific embodiment, there is provided one in which thefirst supply terminal (T1) is configured so as to be capable ofsupplying a power supply voltage based on a wireless power delivery tothe first supply terminal (T1) through a first Schottky diode (D1) andan AC-DC conversion power supply voltage from an AC power supplycoupling interface (24) thereto through a second Schottky diode (D2).

The second supply terminal (T2) is configured so as to be capable ofsupplying a USB power supply voltage from a USB coupling interface (23)to the second supply terminal (T2) (refer to FIG. 2).

[2] A typical embodiment according to another aspect is an operatingmethod of a semiconductor integrated circuit (212) equipped with a firstsupply terminal (T1) capable of supplying a first power supply voltage,a second supply terminal (T2) capable of supplying a second power supplyvoltage, an input voltage selection circuit (2124) coupled to the firstsupply terminal and the second supply terminal, a first, power supplyswitch (SW1, SW2), and a second power supply switch (SW3) (refer to FIG.2).

The input voltage selection circuit (2124) includes a power-on resetcircuit (21244), an input voltage detection circuit (21248) and acontrol circuit (21245, 21246).

The power-on reset circuit (21244) generates a power on reset signal(POR) in response to the supply of the first power supply voltage to thefirst supply terminal (T1) and the supply of the second power supplyvoltage to the second supply terminal (T2).

The input voltage detection circuit (21248) generates a first voltagedetection output signal (Vdet1) in response to the supply of the firstpower supply voltage to the first supply terminal (T1) and generates asecond voltage detection output signal (Vdet2) in response to the supplyof the second power supply voltage to the second supply terminal (T2).

The control circuit (21245, 21246) controls the first power supplyswitch and the second power supply switch in response to the power onreset signal (POR), the first voltage detection output signal (Vdet1)and the second voltage detection output signal (Vdet2).

The input voltage detection circuit (21248) detects the supply of thefirst power supply voltage to the first supply terminal (T1) and thesupply of the second power supply voltage to the second supply terminal(T2) at a timing of a change in the level of the power on reset signal(POR) responsive to the end of a power on reset operation of thepower-on reset circuit (21244).

In a first case where at the timing of the change in the level of thepower on reset signal (POR), the input voltage detection circuit detectsthe supply of the first power supply voltage to the first supplyterminal but does not detect the supply of the second power supplyvoltage to the second supply terminal, the control circuit controls thefirst power supply switch and the second power supply switch to an onstate and an off state respectively after the end of the power on resetoperation (FIGS. 5: S504 and S505).

The first power supply switch and the second power supply switch arerespectively controlled to the on state and the off state after the endof the power on reset operation, so that the first power supply switchcontrolled to the on state supplies the first power supply voltagesupplied to the first supply terminal to a load (3, 26) (FIG. 5: S505).

In a second case where at the timing of the change in the level of thepower on reset signal, the input voltage detection circuit detects thesupply of the second power supply voltage to the second supply terminalbut does not detect the supply of the first power supply voltage to thefirst supply terminal, the control circuit controls the first powersupply switch and the second power supply switch to an off state and anon state respectively after the end of the power on reset operation(FIGS. 5: S506 and S507).

The first power supply switch and the second power supply switch arerespectively controlled to the off state and the on state after the endof the power on reset operation, so that the second power supply switchcontrolled to the on state supplies the second power supply voltagesupplied to the second supply terminal to the load (3, 26) (FIG. 5:S507).

In a third case where at the timing of the change in the level of thepower on reset signal, the input voltage detection circuit detects thesupply of the first power supply voltage to the first supply terminaland the supply of the second power supply voltage to the second supplyterminal, the control circuit controls one of the first power supplyswitch and the second power supply switch and the other thereof to an onstate and an off state respectively after the end of the power on resetoperation (FIGS. 5: S508 and S509).

In the third case, the one of the first power supply switch and thesecond power supply switch and the other thereof are respectivelycontrolled to the on state and the off state in accordance with theorder of precedence set to the control circuit in advance.

The one thereof controlled to the on state supplies the first powersupply voltage or the second power supply voltage supplied to the firstsupply terminal or the second supply terminal to the load (3, 26) (FIG.5: S505).

According to the embodiment, an electronic circuit for automaticallyselecting a power supply to be used out of a plurality of power suppliescan be implemented.

2. Further Detailed Description of the Embodiments

Embodiments will next be explained in further detail. Incidentally, inall of the drawings for explaining the best modes for carrying out theinvention, the same reference numerals are respectively attached tocomponents having the same function as in the drawings, and theirrepetitive description will be omitted.

First Embodiment Configuration of Multifunction Cellular Phone

FIG. 1 is a diagram showing a configuration of a multifunction cellularphone equipped with a semiconductor integrated circuit 212 for batterycharging control, according to a first embodiment.

The multifunction cellular phone shown in FIG. 1 is comprised of a powertransmitting circuit 1, a power receiving circuit 2 and a powerreceiving side system 3. In the multifunction cellular phone shown inFIG. 1 in particular, an RF signal from a power transmitting sideantenna coil 13 is received by a power receiving side antenna coil 25 sothat the charging of a secondary battery 26 and the supply of power tothe power receiving side system 3 are performed.

<<Power Transmitting Circuit on the Transmission Side>>

As shown in FIG. 1, the power transmitting circuit 1 on the transmissionside of a wireless power transmission system is supplied with an ACpower supply through an AC adaptor 10. The power transmitting circuit 1is comprised of a microcontroller unit (MCU) 11 and a power transmissioncontrol circuit 12. The microcontroller unit (MCU) 11 has anauthentication processing function 111 and a cryptographic processingfunction 112. The power transmission control circuit 12 includes arectifier circuit 121 and an RF driver 122. The RF driver 122 is coupledto the power transmitting side antenna coil 13.

A DC power supply voltage generated by rectifying and smoothing the ACpower supply supplied via the AC adaptor 10 by the rectifier circuit 121is supplied to the microcontroller unit (MCU) 11, the RF driver 122 andthe like in the power transmitting circuit 1. The authenticationprocessing function 111 and the cryptographic processing function 112 ofthe microcontroller unit (MCU) 11 in the power transmitting circuit 1respectively perform a mutual authentication process for determiningwhether a user having the multifunction cellular phone corresponding tothe power receiving circuit 2 is a user having a legitimate use right,and etc., and a cryptographic process for preventing interpolation ofcommunication data. That is, the microcontroller unit (MCU) 11 of thepower transmitting circuit 1 performs a key management operation relatedto the generation, retention, renewal, deletion and the like of a cipherkey related to a communication protocol between an authenticationprocessing function 221 and a cryptographic processing function 222 of amicrocontroller unit (MCU) 22 included in the power receiving circuit 2.

As a result, when it is determined by the microcontroller unit (MCU) 11of the power transmitting circuit 1 that the user of the multifunctioncellular phone corresponding to the power receiving circuit 2 is of theuser having the legitimate use right, the RF driver 122 generates an RFdrive signal to be supplied to the power transmitting side antenna coil13 in response to an RF oscillation output signal generated from anunillustrated RF oscillator. Further, communication data related to theauthentication process and cryptographic process from themicrocontroller unit (MCU) 11 of the power transmitting circuit 1 aresupplied to the power receiving circuit 2 through the RF driver 122, thepower transmitting side antenna coil 13 and the power receiving sideantenna coil 25.

<<Power Receiving Circuit on the Reception Side>>

As shown in FIG. 1, the power receiving circuit 2 on the reception sideof the wireless power transmission system is comprised of a powerreception control circuit 21 and the microcontroller unit (MCU) 22. Themicrocontroller unit (MCU) 22 has the authentication processing function221 and the cryptographic processing function 222. The power receptioncontrol circuit 21 includes a rectifier circuit 211 and thesemiconductor integrated circuit 212 for the battery charging control.

In the wireless power transmission system shown in FIG. 1, thecommunications in accordance with the above communication protocol arefirst performed between the microcontroller unit (MCU) 11 of the powertransmitting circuit 1 and the microcontroller unit (MCU) 22 of thepower receiving circuit 2 through the power transmitting side antennacoil 13 and the power receiving side antenna coil 25. For suchcommunications, the power receiving circuit 2 is provided to enableserial communications, the supply of power and the like between thepower reception control circuit 21 and the microcontroller unit (MCU)22. When it is determined by the microcontroller unit (MCU) 11 of thepower transmitting circuit 1 that the user of the multifunction cellularphone corresponding to the power receiving circuit 2 is of the userhaving the legitimate use right, an RF drive signal generated from theRF driver 122 is supplied to the power receiving circuit 2 through thepower transmitting side antenna coil 13 and the power receiving sideantenna coil 25.

A DC power supply voltage generated by allowing the rectifier circuit211 to rectify and smooth the RF drive signal supplied via the powertransmitting side antenna coil 13 and the power receiving side antennacoil 25 is supplied to the semiconductor integrated circuit 212 and themicrocontroller unit (MCU) 22. The DC power supply voltage supplied fromthe rectifier circuit 211 to the semiconductor integrated circuit 212 isused for the charging of the secondary battery 26 and used even for thesupply of power to the power receiving side system 3.

When the power receiving side of the wireless power transmission systemis of a multifunction cellular phone, the power receiving side system 3includes an application processor, a baseband processor, a liquidcrystal display driver IC, an RF signal processing semiconductorintegrated circuit (RFIC), a main memory, non-volatile memories such asa flash memory and so on, etc.

When the power receiving side of the wireless power transmission systemis of a portable personal computer like a tablet PC, the power receivingside system 3 further includes a central processing unit (CPU) and ahard disk replacement type flash memory storage having a massive storagecapacity.

Further, the semiconductor integrated circuit 212 for the batterycharging control and the supply of power to the system can be suppliedwith a USB power supply voltage from a USB coupling interface 23 and anAC-DC conversion power supply voltage generated by rectifying andsmoothing an AC power supply voltage from an AC power supply couplinginterface 24 even other than the DC power supply voltage generated bythe rectifier circuit 211. Accordingly, the semiconductor integratedcircuit 212 for the battery charging control and the system power supplyhas the function of automatically selecting power supply voltages forthe battery charging control and the supply of power to the system outof a plurality of power supply voltages of the DC power supply voltageof the rectifier circuit 211, the USB power supply voltage from the USBcoupling interface 23, and the AC-DC conversion power supply voltagefrom the AC power supply coupling interface 24. Incidentally, USB is anabbreviation of Universal Serial Bus.

<<Configuration of Semiconductor Integrated Circuit for Battery ChargingControl>>

FIG. 2 is a diagram showing a configuration of the semiconductorintegrated circuit 212 for the battery charging control according to thefirst embodiment shown in FIG. 1.

As shown in FIG. 2, the semiconductor integrated circuit 212 for thebattery charging control and the supply of power to the system includesa step-down DC-DC converter 2121, a linear regulator 2122, a USB typedetection circuit 2123, an input voltage detection circuit 2124, anexternal interface 2125, a built-in regulator 2126 and a gate drivecontrol circuit 2127. Further, the semiconductor integrated circuit 212includes a P channel MOS transistor Mp0, and switches SW1, SW2, SW3 andSW4.

A supply terminal T1 for a first input voltage 1 is supplied with apower supply voltage based on a wireless power delivery of the powertransmitting circuit 1 through a first Schottky diode D1 and an AC-DCconversion power supply voltage from the AC power supply couplinginterface 24 through a second Schottky diode D2. A supply terminal T2for a second input voltage 2 is supplied with a USB power supply voltagefrom the USB coupling interface 23. The Schottky diodes D1 and D2respectively function as backflow preventing devices between the powersupply voltage based on the wireless power delivery of the powertransmitting circuit 1 and the AC-DC conversion power supply voltagefrom the AC power supply coupling interface 24 and on the other hand,function as voltage transfer devices which transfer a power supply as aforward voltage low as compared with a PN junction diode. Incidentally,the power supply voltage based on the wireless power delivery of thepower transmitting circuit 1 is a voltage that ranges from 5.5V to 20V.The AC-DC conversion power supply voltage from the AC power supplycoupling interface 24 is a voltage of approximately 7V. The USB powersupply voltage from the USB coupling interface 23 is a voltage of 5V.

An inductor L1 and a capacitor C1 are coupled to the step-down DC-DCconverter 2121 through external terminals DDOUT1 (T5) and DDOUT2 (T6).Thus, the step-down DC-DC converter 2121 operates as a switchingregulator slower in startup at power-on than the linear regulator 2122but has power efficiency higher than the linear regulator 2122. On theother hand, the linear regulator 2122 operates as a series regulatorwhich operates at once immediately after power-on.

That is, the step-down DC-DC converter 2121 and the linear regulator2122 generate a system supply voltage ranging from 3.5V to 5V from thepower supply voltage of 5.5V to 20V for the wireless power delivery ofthe power transmitting circuit 1 or from the AC-DC conversion powersupply voltage of approximately 7V from the AC power supply couplinginterface 24. Thus, the system supply voltage of 5V from the step-downDC-DC converter 2121 and the linear regulator 2122 is supplied to thepower receiving side system 3 through the switches SW2 and SW4 and anexternal terminal SYS (T4). On the other hand, the USB power supplyvoltage of 5V from the USB coupling interface 23 is supplied to thepower receiving side system 3 through the switch SW3 and the externalterminal SYS (T4).

The USB type detection circuit 2123 detects from the bit rate ofdifferential data signals D+ and D− of the USB coupling interface 23 orthe power delivery capability of the supply terminal T2 for the secondinput voltage 2 whether the USB coupling interface 23 corresponds to anyof USB1.1, USB1.0, USB2.0 and USB3.0.

In order to select the operation mode at the start-up, the input voltagedetection circuit 2124 performs the voltage detection of the supplyterminal T1 for the first input voltage 1 and the voltage detection ofthe supply terminal T2 for the second input voltage 2 and furtherperforms on-off control of the switches SW1, SW2, SW3 and SW4 andcontrol of the step-down DC-DC converter 2121, the built-in regulator2126 and the gate drive control circuit 2127. Further, the input voltagedetection circuit 2124 has the function of performing control of the USBtype detection circuit 2123 and supplying USB type detection data outputfrom the USB type detection circuit 2123 to the microcontroller unit(MCU) 22 and the power receiving side system 3 through the externalinterface 2125.

Thus, the external interface 2125 performs interactive communications ofa clock and serial data with the power receiving side system 3 and themicrocontroller unit (MCU) 22.

The built-in regulator 2126 is supplied with the power supply voltagebased on the wireless power delivery of the power transmitting circuit 1via the step-down DC-DC converter 2121 or the linear regulator 2122 orthe AC-DC conversion power supply voltage from the AC power supplycoupling interface 24, or the USB power supply voltage from the USBcoupling interface 23. As a result, an operating voltage V_(DD) 18 of1.8V and an operating voltage V_(DD) 30 of 3.0V are generated from thebuilt-in regulator 2126 and supplied to the microcontroller unit (MCU)22.

The P channel MOS transistor Mp0 is drive-controlled to an on state bythe input voltage detection circuit 2124 and the gate drive controlcircuit 2127 to thereby supply a system supply voltage ranging from 3.5Vto 5V at the external terminal SYS (T4) to the secondary battery 26through an external terminal BAT (T3), whereby the charging of thesecondary battery 26 is performed. For example, the secondary battery 26is a lithium ion battery built in a multifunction cellular phone or thelike, and its charging current becomes a relatively large currentranging from about 0.5 A to about 1.0 A.

Further, the gate drive control circuit 2127 generates an output signalfor driving the gate of the P channel MOS transistor Mp0 in such amanner that the P channel MOS transistor Mp0 is brought into conductionbidirectionally between the external terminal SYS (T4) and the externalterminal BAT (T3). Thus, during the execution of charging of thesecondary battery 26, the charging current of the secondary battery 26flows from the external terminal SYS (T4) to the external terminal BAT(T3). On the other hand, contrary to this, the discharging current ofthe secondary battery 26 flows from the external terminal BAT (T3) tothe external terminal SYS (T4) during a battery operating period by thedischarge of the secondary battery 26. Furthermore, the gate drivecontrol circuit 2127 has the function of performing current control ofcharging and discharging currents during the charging and dischargingoperations of the secondary battery 26 to thereby prevent overchargingand overdischarging.

<<Functions of External Terminals of Semiconductor Integrated Circuit>>

FIG. 3 is a diagram showing the functions of the external terminals ofthe semiconductor integrated circuit 212 for the battery chargingcontrol according to the first embodiment shown in FIG. 2.

As shown in FIG. 3, the external supply terminal for the first inputvoltage 1 has the function of supplying the power supply voltage basedon the wireless power delivery of the power transmitting circuit 1 orthe AC-DC conversion power supply voltage from the AC power supplycoupling interface 24 through the first Schottky diode D1 and the secondSchottky diode D2.

Further, the external supply terminal for the second input voltage 2 hasthe function of supplying the USB power supply voltage from the USBcoupling interface 23.

The external supply terminal for the differential data signal D+ has thefunction of supplying a non-inversion input signal D+ of differentialdata for the USB coupling interface 23.

Further, the external supply terminal for the differential data signalD− has the function of supplying an inversion input signal D− ofdifferential data for the USB coupling interface 23.

The external input/output terminal for the clock has the function ofperforming an interactive communication of the clock for the externalinterface 2125.

In addition, the external input/output terminal for the serial data hasthe function of performing an interactive communication of the serialdata for the external interface 2125.

The external terminal DDOUT1 has the function of outputting a switchingoutput signal based on a switching regulator operation at the step-downDC-DC converter 2121.

Further, the external terminal DDOUT2 has the function of outputting anoutput voltage of the step-down DC-DC converter 2121, which has passedthrough a low-pass filter comprised of the inductor L1 and the capacitorC1.

The external terminal SYS has the function of outputting a power supplyvoltage to the power receiving side system 3.

The external terminal BAT has the function of coupling the secondarybattery 26.

The external terminal V_(DD) 18 has the function of outputting anoperating voltage V_(DD) 18 of 1.8V to the microcontroller (MCU) 22.

The external terminal V_(DD) 30 has the function of outputting anoperating voltage V_(DD) 30 of 3.0V to the microcontroller (MCU) 22.

<<Configuration of Input Voltage Detection Circuit of SemiconductorIntegrated Circuit>>

FIG. 4 is a diagram showing the configuration of the input voltagedetection circuit 2124 for selecting an operation mode at the startup ofthe semiconductor integrated circuit 212 according to the firstembodiment shown in FIG. 2.

As shown in FIG. 4, the input voltage detection circuit 2124 includes alinear regulator 21241, an input voltage selection switch 21242, avoltage comparison/selection circuit 21243, a first reference voltagegenerator Ref_Gen1, a first buffer circuit BA1, a second buffer circuitBA2 and a power-on reset circuit 21244. Further, the input voltagedetection circuit 2124 includes a control logic circuit 21245, an inputvoltage selection switch control logic circuit 21246, a clock generator21247, an input voltage detection circuit 21248 and a gate drive circuit21249.

As shown in the upper left part of FIG. 4, the supply terminal T1 forthe input voltage 1 is supplied with the power supply voltage based onthe wireless power delivery of the power transmitting circuit 1 and theAC-DC conversion power supply voltage from the AC power supply couplinginterface 24. The supply terminal T2 for the second input voltage 2 issupplied with the USB power supply voltage from the USB couplinginterface 23.

The power supply voltage based on the wireless power delivery, havingthe voltage ranging from 5.5V to 20V or the AC-DC conversion powersupply voltage at the supply terminal T1 for the first input voltage 1is converted to an output power supply voltage Vout of approximately 5Vby the linear regulator 21241. The output power supply voltage ofapproximately 5V is supplied to the source of the P channel MOStransistor Mp1 of the input voltage selection switch 21242 and the gatedrive circuit 21249.

The USB power supply voltage from the USB coupling interface 23, havingthe voltage of 5V supplied to the supply terminal T2 for the secondinput voltage 2 is supplied to the source of the P channel MOStransistor Mp2 of the input voltage selection switch 21242.

The gate of the P channel MOS transistor Mp1 of the input voltageselection switch 21242 is driven by a first gate drive output signalMp1_G of the gate drive circuit 21249. The gate of the P channel MOStransistor Mp2 of the input voltage selection switch 21242 is driven bya second gate drive output signal Mp2_G of the gate drive circuit 21249.During a power on rest period to be described in detail below at thepower-on, the first gate drive output signal Mp1_G and the second gatedrive output signal Mp2_G of the gate drive circuit 21249 are both setto a low level. Therefore, the P channel MOS transistor Mp1 and Pchannel MOS transistor Mp2 of the input voltage selection switch 21242are both controlled to an on state.

The voltage comparison/selection circuit 21243 is comprised of a Pchannel MOS transistor Mp3, a P channel MOS transistor Mp4 and adifferential amplifier DA1. Thus, the voltage comparison/selectioncircuit 21243 compares the voltage of a first node Node1 and the voltageof a second node Node2 and thereby selects a high voltage of the twovoltages thereof and generates it as an output voltage Vcc. The firstnode Node1 is coupled to the drain of the P channel MOS transistor Mp3and an inversion input terminal − of the differential amplifier DA1. Thesecond node Node2 is coupled to the drain of the P channel MOStransistor Mp4 and a non-inversion input terminal + of the differentialamplifier DA1. A non-inversion output terminal + and an inversion outputterminal − of the differential amplifier DA1 are respectively coupled tothe gate of the P channel MOS transistor Mp3 and the gate of the Pchannel MOS transistor Mp4. The source of the P channel MOS transistorMp3 and the source of the P channel MOS transistor Mp4 are coupled incommon to generate the output voltage Vcc.

The output voltage Vcc of the voltage comparison/selection circuit 21243is supplied to the differential amplifier DA1, the first referencevoltage generator Ref_Gen1, the first buffer circuit BA1 and the secondbuffer circuit BA2 as an operating power supply voltage.

The first reference voltage generator Ref_Gen1 allows the output voltageVcc output from the voltage comparison/selection circuit 21243 tofunction as an operating power supply voltage to thereby generate areference voltage V_(REF).

The first buffer circuit BA1 and the second buffer circuit BA2respectively generate an analog circuit power supply voltage AV_(DD) anda digital circuit power supply voltage DV_(DD) proportional to the levelof the reference voltage V_(REF) in response to the reference voltageV_(REF) generated from the first reference voltage generator Ref_Gen1.

The power-on reset circuit 21244 is comprised of a second referencevoltage generator Ref_Gen2, a differential amplifier DA2, a resistor Rp,a capacitor Cp and a third buffer circuit BA3. The second referencevoltage generator Ref_Gen2 and differential amplifier DA2 of thepower-on reset circuit 21244 are supplied with the digital circuit powersupply voltage DV_(DD) generated by the second buffer circuit BA2. Anon-inversion input terminal + and inversion input terminal − of thedifferential amplifier DA2 are respectively supplied with the digitalcircuit power supply voltage DV_(DD) and a reference voltage V_(BB)generated from the second reference voltage generator Ref_Gen2.

An output voltage of the differential amplifier DA2 of the power-onreset circuit 21244 is supplied to one end of the resistor Rp. The otherend of the resistor Rp is coupled to one end of the capacitor Cp and aninput terminal of the third buffer circuit BA3. The other end of thecapacitor Cp is coupled to a ground potential. A power on reset signalPOR of a low level generated from the third buffer circuit BA3 duringthe power on reset period is supplied to an inversion reset inputterminal/Reset of the control logic circuit 21245 and an inversion resetinput terminal/Reset of the input voltage selection switch control logiccircuit 21246.

A clock signal generated from the clock generator 21247 supplied withthe output voltage Vcc delivered from the voltage comparison/selectioncircuit 21243 and the digital circuit power supply voltage DV_(DD)delivered from the second buffer circuit BA2 is supplied to a clockinput terminal CLK of the control logic circuit 21245 and a clock inputterminal CLK of the input voltage selection switch control logic circuit21246.

The control logic circuit 21245 of the input voltage detection circuit2124 controls the whole operation of the semiconductor integratedcircuit 212 according to the first embodiment shown in FIG. 2. That is,an analog circuit 2128 coupled to the input voltage detection circuit2124 shown in FIG. 4 includes analog circuits of the step-down DC-DCconverter 2121, linear regulator 2122, USB type detection circuit 2123,built-in regulator 2126 and gate drive control circuit 2127 of thesemiconductor integrated circuit 212 shown in FIG. 2. Thus, theoperations of these analog circuits are all controlled by the controllogic circuit 21245 of the input voltage detection circuit 2124 shown inFIG. 4. Incidentally, the analog circuit 2128 is supplied with theoutput voltage Vcc delivered from the voltage comparison/selectioncircuit 21243 and the analog circuit power supply voltage AV_(DD) outputfrom the first buffer circuit BA1.

Further, likewise, the operation of the input voltage selection switchcontrol logic circuit 21246 is also controlled by the control logiccircuit 21245 of the input voltage detection circuit 2124 shown in FIG.4.

Furthermore, likewise, the operations of the switches SW1, SW2, SW3 andSW4, built-in regulator 2126 and gate drive control circuit 2127 shownin FIG. 2 are also controlled by the control logic circuit 21245 of theinput voltage detection circuit 2124 shown in FIG. 4.

The input voltage detection circuit 21248 is supplied with the outputvoltage Vcc delivered from the voltage comparison/selection circuit21243 and the analog circuit power supply voltage AV_(DD) output fromthe first buffer circuit BA1. After the elapse of the power on resetperiod, the input voltage detection circuit 21248 detects the level ofthe power supply voltage based on the wireless power delivery or AC-DCconversion at the supply terminal T1 for the first input voltage 1, andthe level of the USB power supply voltage at the supply terminal T2 forthe second input voltage 2. As a result, voltage detection outputsignals Vdet1 and Vdet2 of 2 bits output from the input voltagedetection circuit 21248 are supplied to the control logic circuit 21245and the input voltage selection switch control logic circuit 21246. Thatis, the voltage detection output signal Vdet1 indicates a result ofdetection of the presence or absence of the supply of the power supplyvoltage based on the wireless power delivery or AC-DC conversion to thesupply terminal T1 for the first input voltage 1. Also the voltagedetection output signal Vdet2 indicates a result of detection of thepresence or absence of the supply of the USB power supply voltage to thesupply terminal T2 for the second input voltage 2.

After the elapse of the power on reset period, one of the first gatedrive output signal Mp1_G and second gate drive output signal Mp2_G ofthe gate drive circuit 21249 and the other thereof are respectively setto a low level and a high level by signals output from the input voltageselection switch control logic circuit 21246 that has responded to the2-bit voltage detection output signals Vdet1 and Vdet2, whereby theautomatic selection of a power supply to be used is carried out.

Consider where the supply of the power supply voltage to the supplyterminal T1 for the first input voltage 1 is detected by the high-levelvoltage detection output signal Vdet1, and the non-supply of the powersupply voltage to the supply terminal T2 for the second input voltage 2is detected by the low-level voltage detection output signal Vdet2. Inthis case, in response to the voltage detection output signals Vdet1 andVdet2 different in level, the control logic circuit 21245 controls theswitch SW2 lying inside the semiconductor integrated circuit 212according to the first embodiment shown in FIG. 2 to an on state and onthe other hand, controls the switch SW3 to an off state. As a result,the voltage supplied from the supply terminal T1 for the first inputvoltage 1 is used for the charging of the secondary battery 26 via thestep-down DC-DC converter 2121, the switch SW2 and the P channel MOStransistor Mp0 and used for the supply of power to the power receivingside system 3. Further, in this case, the gate drive circuit 21249 setsthe first gate drive output signal Mp1_G and the second gate driveoutput signal Mp2_G to low and high levels respectively. In addition,the voltage comparison/selection circuit 21243 detects that the voltageof the first node Node1 is higher than that of the second node Node2 andgenerates the voltage of the first node Node1 supplied from the supplyterminal T1 for the first input voltage 1, as the output voltage Vcc ofthe voltage comparison/selection circuit 21243.

Consider where the non-supply of the power supply voltage to the supplyterminal T1 for the first input voltage 1 is detected by the low-levelvoltage detection output signal Vdet1, and the supply of the powersupply voltage to the supply terminal T2 for the second input voltage 2is detected by the high-level voltage detection output signal Vdet2. Inthis case, in response to the voltage detection output signals Vdet1 andVdet2 different in level, the control logic circuit 21245 controls theswitch SW2 lying inside the semiconductor integrated circuit 212according to the first embodiment shown in FIG. 2 to an off state and onthe other hand, controls the switch SW3 to an on state. As a result, thevoltage supplied from the supply terminal T2 for the second inputvoltage 2 is used for the charging of the secondary battery 26 via theswitch SW3 and the P channel MOS transistor Mp0 and used for the supplyof power to the power receiving side system 3. Further, in this case,the gate drive circuit 21249 sets the first gate drive output signalMp1_G and the second gate drive output signal Mp2_G to high and lowlevels respectively. In addition, the voltage comparison/selectioncircuit 21243 detects that the voltage of the second node Node2 ishigher that that of the first node Node1 and generates the voltage ofthe second node Node2 supplied from the supply terminal T2 for thesecond input voltage 2, as the output voltage Vcc of the voltagecomparison/selection circuit 21243.

Consider where the supply of the power supply voltage based on thewireless power delivery or AC-DC conversion to the supply terminal T1for the first input voltage 1 and the supply of the USB power supplyvoltage to the supply terminal T2 for the second input voltage 2 aresimultaneously detected by the 2-bit voltage detection output signalsVdet1 and Vdet2 of the input voltage detection circuit 21248. In thiscase, in response to the voltage detection output signals Vdet1 andVdet2 both high in level, the control logic circuit 21245 adjusts thelevel of the output power supply voltage Vout of approximately 5V of thelinear regulator 21241.

That is, when the supply voltage of the supply terminal T1 for the firstinput voltage 1, which has been detected simultaneously with the supplyvoltage of the supply terminal T2 for the second input voltage 2, takesprecedence over the supply voltage of the supply terminal T2 for thesecond input voltage 2, the output power supply voltage Vout ofapproximately 5V of the linear regulator 21241 is set to, for example,5.2V higher than the USB power supply voltage from the USB couplinginterface 23, having the voltage of 5V supplied to the supply terminalT2 for the second input voltage 2. Further, the first gate drive outputsignal Mp1_G and second gate drive output signal Mp2_G of the gate drivecircuit 21249 controlled by the control logic circuit 21245 are set tolow and high levels respectively. As a result, the voltagecomparison/selection circuit 21243 detects that the voltage of the firstNode1 is higher than that of the second node Node2 and generates thesupply voltage of the supply terminal T1 for the first input voltage 1as the output voltage Vcc of the voltage comparison/selection circuit21243. Further, the control logic circuit 21245 controls the switch SW2lying inside the semiconductor integrated circuit 212 according to thefirst embodiment shown in FIG. 2 to an on state and on the other hand,controls the switch SW3 to an off state. As a result, the voltagesupplied from the supply terminal T1 for the first input voltage 1 isused for the charging of the secondary battery 26 through the step-downDC-DC converter 2121, the switch SW2 and the P channel MOS transistorMp0 and used for the supply of power to the power receiving side system3.

Contrary to this, when the supply voltage of the supply terminal T2 forthe second input voltage 2 takes higher priority than the supply voltageof the supply terminal T1 for the first input voltage 1, the outputpower supply voltage Vout of approximately 5V of the linear regulator21241 is set to, for example, 4.8V lower than the USB power supplyvoltage from the USB coupling interface 23, having the voltage of 5Vsupplied to the supply terminal T2 for the second input voltage 2.Further, the first gate drive output signal Mp1_G and second gate driveoutput signal Mp2_G of the gate drive circuit 21249 controlled by thecontrol logic circuit 21245 are set to high and low levels respectively.As a result, the voltage comparison/selection circuit 21243 detects thatthe voltage of the second Node2 is higher than that of the first NodeNode1 and generates the voltage of the second node Node2 from the supplyterminal T2 for the second input voltage 2 as the output voltage Vcc ofthe voltage comparison/selection circuit 21243. Further, the controllogic circuit 21245 controls the switch SW2 lying inside thesemiconductor integrated circuit 212 according to the first embodimentshown in FIG. 2 to an off state and on the other hand, controls theswitch SW3 to an on state. As a result, the voltage supplied from thesupply terminal T2 for the second input voltage 2 is used for thecharging of the secondary battery 26 through the switch SW3 and the Pchannel MOS transistor Mp0 and used for the supply of power to the powerreceiving side system 3.

On the other hand, before the elapse of the power on reset period, thefirst gate drive output signal Mp1_G and second gate drive output signalMp2_G of the gate drive circuit 21249 are both set to the low level bythe output signal of the input voltage selection switch control logiccircuit 21246 that has responded to the low-level power on reset signalPOR. As a result, the P channel MOS transistor Mp1 and the P channel MOStransistor Mp2 included in the input voltage selection switch 21242 areboth controlled to an on state.

<<Automatic Selecting Operation of Used Voltage>>

FIG. 5 is a diagram showing the operation of automatically selecting apower supply to be used from a plurality of power supplies by thesemiconductor integrated circuit 212 according to the first embodimentshown in FIGS. 2 and 4.

As shown in Step S500 of FIG. 5, in an initial setting state before thepower supply voltages are supplied to the supply terminal T1 for thefirst input voltage 1 and the supply terminal T2 for the second inputvoltage 2, the first gate drive output signal Mp1_G and second gatedrive output signal Mp2_G of the gate drive circuit 21249 are both setto a low level. As a result, the P channel MOS transistor Mp1 and Pchannel MOS transistor Mp2 of the input voltage selection switch 21242are both controlled to an on state.

At the next Step S501, at least either of the supply terminal T1 for thefirst input voltage 1 and the supply terminal T2 for the second inputvoltage 2 is supplied with the power supply voltage. That is, the supplyterminal T1 for the first input voltage 1 is supplied with the powersupply voltage based on the wireless power delivery of the powertransmitting circuit 1 and the AC-DC conversion power supply voltagefrom the AC power supply coupling interface 24. Alternatively, thesupply terminal T2 for the second input voltage 2 is supplied with theUSB power supply voltage from the USB coupling interface 23.

At the next Step S502, since the digital circuit power supply voltageDV_(DD) rises in response to the supply of power at Step S501, the poweron reset operation by the power-on reset circuit 21244 is performed.

When the power on reset operation at Step S502 is ended, the detectionof a plurality of power supply voltages is performed at the next StepS503. That is, at Step S503, the input voltage detection circuit 21248detects the level of the power supply voltage based on the wirelesspower delivery or AC-DC conversion at the supply terminal T1 for thefirst input voltage 1 and the level of the USB power supply voltage ofthe supply terminal T2 for the second input voltage 2. As a result,voltage detection output signals Vdet1 and Vdet2 of two bits aregenerated from the input voltage detection circuit 21248. The voltagedetection output signal Vdet1 indicates a result of detection of thepresence or absence of the supply of the power supply voltage based onthe wireless power delivery or AC-DC conversion to the supply terminalT1 for the first input voltage 1. The voltage detection output signalVdet2 indicates a result of detection of the presence or absence of thesupply of the USB power supply voltage to the supply terminal T2 for thesecond input voltage 2.

When, upon the detection of the power supply voltages at above StepS503, only the supply of the power supply voltage to the supply terminalT1 for the first input voltage 1 is detected, and the supply of thepower supply voltage to the supply terminal T2 for the second inputvoltage 2 is not detected, the process for the automatic selectingoperation proceeds to Step S504.

That is, at the next Step S505, the gate drive circuit 21249 sets thefirst gate drive output signal Mp1_G and the second gate drive outputsignal Mp2_G to low and high levels respectively in response to thedetection of only the wireless power delivery at Step S504. Thus, sincethe P channel MOS transistor Mp1 and P channel MOS transistor Mp2 of theinput voltage selection switch 21242 are respectively controlled to theon and off states, the initial operation of the wireless power deliveryis started. Further, at this Step S505, the control logic circuit 21245controls the switch SW2 lying inside the semiconductor integratedcircuit 212 according to the first embodiment shown in FIG. 2 to an onstate and on the other hand, controls the switch SW3 to an off state.Thus, the supply voltage based on the wireless power delivery from thesupply terminal T1 for the first input voltage 1 is used for thecharging of the secondary battery 26 through the step-down DC-DCconverter 2121, the switch SW2 and the P channel MOS transistor Mp0 andused for the supply of power to the power receiving side system 3.

When, upon the detection of the power supply voltages at above StepS503, only the supply of the power supply voltage to the supply terminalT2 for the second input voltage 2 is detected, and the supply of thepower supply voltage to the supply terminal T1 for the first inputvoltage 1 is not detected, the process for the automatic selectingoperation proceeds to Step S506.

That is, at the next Step S507, the gate drive circuit 21249 sets thefirst gate drive output signal Mp1_G and the second gate drive outputsignal Mp2_G to high and low levels respectively in response to thedetection of only the USB power delivery at Step S506. Thus, since the Pchannel MOS transistor Mp1 and P channel MOS transistor Mp2 of the inputvoltage selection switch 21242 are respectively controlled to the offand on states, the initial operation of the USB power delivery isstarted. Further, at this Step S507, the control logic circuit 21245controls the switch SW2 lying inside the semiconductor integratedcircuit 212 according to the first embodiment shown in FIG. 2 to an offstate and on the other hand, controls the switch SW3 to an on state.Thus, the supply voltage based on the USB power delivery from the supplyterminal T2 for the second input voltage 2 is used for the charging ofthe secondary battery 26 through the switch SW3 and the P channel MOStransistor Mp0 and used for the supply of power to the power receivingside system 3.

When, upon the detection of the power supply voltages at above StepS503, both of the supply of the power supply voltage to the supplyterminal T1 for the first input voltage 1 and the supply of the powersupply voltage to the supply terminal T2 for the second input voltage 2are detected, the process for the automatic selecting operation proceedsto Step S508.

That is, at the next Step S509, in response to the detection of both ofthe wireless power delivery and the USB power delivery at Step S508, thegate drive circuit 21249 sets the first gate drive output signal Mp1_Gand the second gate drive output signal Mp2_G to low and high levelsrespectively to give higher priority to the wireless power delivery thanthe USB power delivery. Accordingly, since the P channel MOS transistorMp1 and P channel MOS transistor Mp2 of the input voltage selectionswitch 21242 are respectively controlled to the on and off states, theinitial operation of the wireless power delivery is started. Further, atthis Step S509, the control logic circuit 21245 controls the switch SW2lying inside the semiconductor integrated circuit 212 according to thefirst embodiment shown in FIG. 2 to an on state and on the other hand,controls the switch SW3 to an off state. Accordingly, the supply voltagebased on the wireless power delivery from the supply terminal T1 for thefirst input voltage 1 is used for the charging of the secondary battery26 through the step-down DC-DC converter 2121, the switch SW2 and the Pchannel MOS transistor Mp0 and used for the supply of power to the powerreceiving side system 3. Thus, the reason why the wireless powerdelivery is given priority over the USB power delivery at Step S509, isthat the current drive capability of the wireless power delivery fromthe power receiving circuit 2 through the power transmitting sideantenna coil 13 and the power receiving side antenna coil 25 isgenerally higher than that of the USB coupling interface 23.

Second Embodiment Another Operation of Automatically Selecting Voltageto be Used

FIG. 6 is a diagram showing the operation of automatically selecting aused power supply out of a plurality of power supplies by thesemiconductor integrated circuit 212 according to a second embodimentshown in FIGS. 2 and 4.

The semiconductor integrated circuit 212 according to the firstembodiment shown in FIGS. 2 and 4 has carried out the initial operationof first automatically selecting the power supply to be used out of thepower supplies as shown in FIG. 5.

The semiconductor integrated circuit 212 according to the secondembodiment shown in FIGS. 2 and 4 to be next described is capable of, asshown in FIG. 6, performing an initial operation of first automaticallyselecting a used power supply from a plurality of power supplies andperforming a succeeding operation of further automatically selecting aused voltage even upon the additional supply of subsequent power supplyvoltages.

Since the contents of operations at respective Steps S500 through S509shown in FIG. 6 according to the second embodiment are exactly the sameas the contents of the operations at the respective Steps S500 throughS509 described in FIG. 5 according to the first embodiment, theirdescription will be omitted.

After the initial operation of the wireless power delivery at Step S505shown in FIG. 6, a USB power supply voltage from the USB couplinginterface 23 to the supply terminal T2 for the second input voltage 2 issupplied at the next Step S600. As a result, at this Step S600, thedetection of the USB power delivery is added after the detection of thewireless power delivery.

At the next Step S601 subsequent to the additional detection of the USBpower delivery at Step S600, the gate drive circuit 21249 sets a firstgate drive output signal Mp1_G and a second gate drive output signalMp2_G to low and high levels respectively to give higher priority to thewireless power delivery than the USB power delivery exactly as with StepS509 of FIG. 5 according to the first embodiment. Accordingly, at StepS601, the P channel MOS transistor Mp1 and P channel MOS transistor Mp2of the input voltage selection switch 21242 are respectively controlledto an on state and an off state. The continuous operation of thewireless power delivery is therefore started. Further, at this StepS601, the control logic circuit 21245 holds the switch SW2 lying insidethe semiconductor integrated circuit 212 according to the firstembodiment shown in FIG. 2 in an on state and on the other hand, holdsthe switch SW3 in an off state. Accordingly, the supply voltage based onthe wireless power delivery from the supply terminal T1 for the firstinput voltage 1 is used for the charging of the secondary battery 26through the step-down DC-DC converter 2121, the switch SW2 and the Pchannel MOS transistor Mp0 and used for the supply of power to the powerreceiving side system 3. Thus, the reason why the wireless powerdelivery is given higher priority than the USB power delivery even atStep S601 is that the current drive capability of the wireless powerdelivery from the power receiving circuit 2 through the powertransmitting side antenna coil 13 and the power receiving side antennacoil 25 shown in FIG. 1 is generally higher than that of the USBcoupling interface 23.

After the initial operation of the USB power delivery at Step S507 shownin FIG. 6, a power supply voltage based on the wireless power deliveryof the power transmitting circuit 1 to the supply terminal T1 for thefirst input voltage 1 is supplied at the next Step S602. As a result, atthis Step S602, the detection of the wireless power delivery is addedafter the detection of the USB power delivery.

At the next Step S603 subsequent to the additional detection of thewireless power delivery at Step S602, the gate drive circuit 21249changes the first gate drive output signal Mp1_G from the high to lowlevels and changes the second gate drive output signal Mp2_G from thelow to high levels to give higher priority to the wireless powerdelivery than the USB power delivery. As a result, at Step S603, theoperation of switching from the USB power delivery to the wireless powerdelivery is executed. At this Step S603, the control logic circuit 21245changes the switch SW2 lying inside the semiconductor integrated circuit212 according to the first embodiment shown in FIG. 2 from the off to onstate and on the other hand, changes the switch SW3 from the on to offstate. As a result, the supply voltage based on the wireless powerdelivery from the supply terminal T1 for the first input voltage 1 isused for the charging of the secondary battery 26 through the step-downDC-DC converter 2121, the switch SW2 and the P channel MOS transistorMp0 and used for the supply of power to the power receiving side system3. Thus, the reason why the wireless power delivery is given higherpriority than the USB power delivery even at Step S603 is that thecurrent drive capability of the wireless power delivery from the powerreceiving circuit 2 through the power transmitting side antenna coil 13and the power receiving side antenna coil 25 is generally higher thanthat of the USB coupling interface 23.

After the initial operation of the wireless power delivery at Step S509shown in FIG. 6, a USB power supply voltage from the USB couplinginterface 23 to the supply terminal T2 for the second input voltage 2 issupplied at the next Step S604. As a result, at this Step S604, theredetection of the USB power delivery is added after the detection ofthe wireless power delivery.

At the next Step S605 subsequent to the redetection of the USB powerdelivery at Step S604, the gate drive circuit 21249 sets the first gatedrive output signal Mp1_G and the second gate drive output signal Mp2_Gto low and high levels respectively to give higher priority to thewireless power delivery than the USB power delivery exactly as with StepS509 of FIG. 5 according to the first embodiment. Accordingly, at StepS605, the P channel MOS transistor Mp1 and P channel MOS transistor Mp2of the input voltage selection switch 21242 are respectively controlledto an on state and an off state. The continuous operation of thewireless power delivery is therefore started. Further, at this StepS605, the control logic circuit 21245 holds the switch SW2 lying insidethe semiconductor integrated circuit 212 according to the firstembodiment shown in FIG. 2 in an on state and on the other hand, holdsthe switch SW3 in an off state. Accordingly, the supply voltage based onthe wireless power delivery from the supply terminal T1 for the firstinput voltage 1 is used for the charging of the secondary battery 26through the step-down DC-DC converter 2121, the switch SW2 and the Pchannel MOS transistor Mp0 and used for the supply of power to the powerreceiving side system 3. Thus, the reason why the wireless powerdelivery is given higher priority than the USB power delivery even atStep S601 is that the current drive capability of the wireless powerdelivery from the power receiving circuit 2 through the powertransmitting side antenna coil 13 and the power receiving side antennacoil 25 shown in FIG. 1 is generally higher than that of the USBcoupling interface 23.

<<Waveform Diagrams of Respective Parts in Semiconductor IntegratedCircuit>>

FIG. 7 is a diagram showing the waveforms of the respective parts in thesemiconductor integrated circuit 212 according to the second embodimentshown in FIGS. 2 and 4 at Steps S506, S507, S602 and S603 in theoperation of automatically selecting the used power supply out of thepower supplies according to the second embodiment shown in FIG. 6.

As shown in FIG. 7, a rise in the USB power supply voltage of the supplyterminal T2 for the second input voltage 2 is started by the supply ofthe power supply voltage to the supply terminal T2 for the second inputvoltage 2 at Step S506. When the rise in the USB power supply voltagereaches a second detection threshold voltage, a voltage detection outputsignal Vdet2 of the input voltage detection circuit 21248 changes from alow to high levels.

A rise in the output voltage Vcc of the voltage comparison/selectioncircuit 21243 is started in response to the rise in the USB power supplyvoltage. Further, a rise in the digital circuit power supply voltageDV_(DD) generated from the second buffer circuit BA2 is started inresponse to the rise in the output voltage Vcc of the voltagecomparison/selection circuit 21243. When the digital circuit powersupply voltage DV_(DD) reaches a third detection threshold voltagecorresponding to the reference voltage V_(BB) of the second referencevoltage generator Ref_Gen2, the output of the differential amplifier DA2of the power-on reset circuit 21244 changes from a low to high levels,so that a power on reset period based on the charge of a resistor Rp anda capacitor Cp in a time constant circuit is started. When the terminalvoltage Vc applied across the capacitor Cp of the time constant circuitreaches a fourth detection threshold voltage corresponding to thethreshold voltage of the third buffer circuit BA3, a power on resetsignal POR changes from a low to high levels so that the power on resetoperation of the control logic circuit 21245 and the input voltageselection switch control logic circuit 21246 is completed.

With the end of the power on reset operation, the input voltagedetection circuit 21248 is responsive to the low-level voltage detectionoutput signal Vdet1 and high-level voltage detection output signal Vdet2of the input voltage detection circuit 21248. Accordingly, the firstgate drive output signal Mp1_G and the second gate drive output signalMp2_G are respectively set to high and low levels by control made by theinput voltage selection switch control logic circuit 21246 and the gatedrive circuit 21249. Accordingly, since the P channel MOS transistor Mp1and P channel MOS transistor Mp2 of the input voltage selection switch21242 are respectively controlled to off and on states, the wirelesspower delivery is controlled to an off state, and the USB power deliveryis controlled to an on state, whereby the automatic selection of thepower supply to be used is performed.

In this state, a rise in the power supply voltage based on the wirelesspower delivery from the supply terminal T1 for the first input voltage 1is started by the supply of the power supply voltage to the supplyterminal T1 for the first input voltage 1 at Step S602 of FIG. 6. Whenthe rise in the power supply voltage based on the wireless powerdelivery reaches a first detection threshold voltage, the voltagedetection output signal Vdet1 of the input voltage detection circuit21248 changes from a low to high levels.

In response to both high-level voltage detection output signals Vdet1and Vdet2 of the input voltage detection circuit 21248, an input voltageswitching indication signal supplied from the control logic circuit21245 to the input voltage selection switch control logic circuit 21246changes from a low to high levels. With the control made by the inputvoltage selection switch control logic circuit 21246 and the gate drivecircuit 21249 responsive to the change of the input voltage switchingindication signal from the low level to the high level, the first gatedrive output signal Mp1_G changes from a high to low levels and on theother hand, the second gate drive output signal Mp2_G changes from a lowto high levels. As a result, in the input voltage selection switch21242, the P channel MOS transistor Mp1 is changed from an off state toan on state, whereas the P channel MOS transistor Mp2 is changed from anon state to an off state. Further, since the switch SW2 lying inside thesemiconductor integrated circuit 212 is brought to an on state and theswitch SW3 is brought to an off state, the USB power delivery low inpriority is controlled to an off state, and the wireless power deliveryhigh in priority is controlled to an on state.

Third Embodiment Another Automatic Selecting Operation of Voltage to beUsed

FIG. 8 is a diagram showing the operation of automatically selecting aused power supply out of a plurality of power supplies by thesemiconductor integrated circuit 212 according to a third embodimentshown in FIGS. 2 and 4.

The operation of automatically selecting the used power supply from thepower supplies according to the second embodiment shown in FIG. 6 has anadvantage that the operation can approximately perfectly be carried outinside the semiconductor integrated circuit 212 according to the secondembodiment shown in FIGS. 2 and 4, but on the other hand has a problemthat the degree of freedom of the automatic selection is low. That is,battery-operated cellular electronic devices such as a multifunctioncellular phone, a tablet PC, etc. need to improve the degree of freedomof the operation of automatic selection of the used power supply fromthe power supplies for the purpose of coping with user's various ideas.

The operation of automatic selection of the used power supply from thepower supplies according to the third embodiment shown in FIG. 8 iscapable of improving the degree of freedom by a program to thenon-volatile memory or the like of the power receiving side system 3coupled to the semiconductor integrated circuit 212 according to thethird embodiment shown in FIGS. 2 and 4. That is, since the non-volatilememory such as the flash memory or the like is coupled to theapplication processor and the baseband processor of the power receivingside system 3, the degree of freedom of the operation of automaticselection of a used power supply from a plurality of power supplies canbe improved using the non-volatile memory.

Since the contents of operations at respective steps from Steps S500through S604 shown in FIG. 8 according to the third embodiment areexactly the same as the contents of the operations at the respectivesteps from Steps S500 through S604 described in FIG. 6 according to thesecond embodiment, their description will omitted.

After the additional detection of the USB power delivery at Step S600shown in FIG. 8, at the next Step S800, information about the additionaldetection of the USB power delivery at this Step S600 is notified fromthe semiconductor integrated circuit 212 to the application processorand baseband processor of the power receiving side system 3 through theexternal interface 2125.

At the next Step S801 after the notification to the power receiving sidesystem 3 at Step S800, indication information indicative of the presenceor absence of switching between the USB power delivery and the wirelesspower delivery is outputted from the application processor or thebaseband processor or the like of the power receiving side system 3.

When the indication information indicative of the switching from thewireless power delivery to the USB power delivery is outputted at StepS801, the gate drive circuit 21249 sets a first gate drive output signalMp1_G and a second gate drive output signal Mp2_G to high and low levelsrespectively at the next Step S802. Accordingly, since the P channel MOStransistor Mp1 and P channel MOS transistor Mp2 of the input voltageselection switch 21242 are respectively controlled to an off state andan on state, the operation of switching from the wireless power deliveryto the USB power delivery is performed. Further, at this Step S802, thecontrol logic circuit 21245 changes the switch SW2 lying inside thesemiconductor integrated circuit 212 according to the third embodimentshown in FIG. 2 from an on state to an off state and on the other hand,changes the switch SW3 from an off state to an on state. Accordingly,the supply voltage based on the USB power delivery from the supplyterminal T2 for the second input voltage 2 is used for the charging ofthe secondary battery 26 through the step-down DC-DC converter 2121, theswitch SW2 and the channel MOS transistor Mp0 and used for the supply ofpower to the power receiving side system 3.

On the other hand, when non-switching indication information indicativeof non-switching from the wireless power delivery to the USB powerdelivery is outputted at Step S801, the process for the automaticselecting operation is returned to Step S505, where the gate drivecircuit 21249 holds the first gate drive output signal Mp1_G and thesecond gate drive output signal Mp2_G in the low and high levelsrespectively. Accordingly, since the P channel MOS transistor Mp1 and Pchannel MOS transistor Mp2 of the input voltage selection switch 21242are respectively maintained in an on state and an off state, the initialoperation of the wireless power delivery is maintained. Further, at thisStep S505, the control logic circuit 21245 maintains the switch SW2lying inside the semiconductor integrated circuit 212 according to thethird embodiment shown in FIG. 2 in an on state and on the other hand,holds the switch SW3 in an off state. Accordingly, the supply voltagebased on the wireless power delivery from the supply terminal T1 for thefirst input voltage 1 is used for the charging of the secondary battery26 through the step-down DC-DC converter 2121, the switch SW2 and the Pchannel MOS transistor Mp0 and used for the supply of power to the powerreceiving side system 3.

After the additional detection of the wireless power delivery at StepS602 shown in FIG. 8, at the next Step S803, information about theadditional detection of the wireless power delivery at this Step S602 isnotified from the semiconductor integrated circuit 212 to theapplication processor and baseband processor of the power receiving sidesystem 3 through the external interface 2125.

At the next Step S804 after the notification to the power receiving sidesystem 3 at Step S803, indication information indicative of the presenceor absence of switching between the USB power delivery and the wirelesspower delivery is outputted from the application processor or thebaseband processor or the like of the power receiving side system 3.

When the indication information indicative of the switching from the USBpower delivery to the wireless power delivery is outputted at Step S804,the gate drive circuit 21249 sets the first gate drive output signalMp1_G and the second gate drive output signal Mp2_G to low and highlevels respectively at the next Step S805. Accordingly, since the Pchannel MOS transistor Mp1 and P channel MOS transistor Mp2 of the inputvoltage selection switch 21242 are respectively controlled to an onstate and an off state, the operation of switching from the USB powerdelivery to the wireless power delivery is performed. Further, at thisStep S805, the control logic circuit 21245 changes the switch SW2 lyinginside the semiconductor integrated circuit 212 according to the thirdembodiment shown in FIG. 2 from an off state to an on state and on theother hand, changes the switch SW3 from an on state to an off state.Accordingly, the supply voltage based on the wireless power deliveryfrom the supply terminal T1 for the first input voltage 1 is used forthe charging of the secondary battery 26 through the step-down DC-DCconverter 2121, the switch SW2 and the P channel MOS transistor Mp0 andused for the supply of power to the power receiving side system 3.

On the other hand, when non-switching indication information indicativeof non-switching from the USB power delivery to the wireless powerdelivery is outputted at Step S804, the process for the automaticselecting operation is returned to Step S507, where the gate drivecircuit 21249 holds the first gate drive output signal Mp1_G and thesecond gate drive output signal Mp2_G to high and low levelsrespectively. Accordingly, since the P channel MOS transistor Mp1 and Pchannel MOS transistor Mp2 of the input voltage selection switch 21242are respectively maintained in an off state and an on state, the initialoperation of the USB power delivery is maintained. Further, at this StepS507, the control logic circuit 21245 maintains the switch SW2 lyinginside the semiconductor integrated circuit 212 according to the thirdembodiment shown in FIG. 2 in an off state and on the other hand, holdsthe switch SW3 in an on state. Accordingly, the supply voltage based onthe USB power delivery from the supply terminal T2 for the second inputvoltage 2 is used for the charging of the secondary battery 26 throughthe step-down DC-DC converter 2121, the switch SW2 and the P channel MOStransistor Mp0 and used for the supply of power to the power receivingside system 3.

After the additional detection of the USB power delivery at Step S604shown in FIG. 8, at the next Step S806, information about the additionaldetection of the USB power delivery at this Step S604 is notified fromthe semiconductor integrated circuit 212 to the application processorand baseband processor of the power receiving side system 3 through theexternal interface 2125.

At the next Step S807 after the notification to the power receiving sidesystem 3 at Step S806, indication information indicative of the presenceor absence of switching between the USB power delivery and the wirelesspower delivery is outputted from the application processor or thebaseband processor or the like of the power receiving side system 3.

When the indication information indicative of the switching from thewireless power delivery to the USB power delivery is outputted at StepS807, the gate drive circuit 21249 sets the first gate drive outputsignal Mp1_G and the second gate drive output signal Mp2_G to high andlow levels respectively at the next Step S808. Accordingly, since the Pchannel MOS transistor Mp1 and P channel MOS transistor Mp2 of the inputvoltage selection switch 21242 are respectively controlled to an offstate and an on state, the operation of switching from the wirelesspower delivery to the USB power delivery is performed. Further, at thisStep S808, the control logic circuit 21245 changes the switch SW2 lyinginside the semiconductor integrated circuit 212 according to the thirdembodiment shown in FIG. 2 from an on state to an off state and on theother hand, changes the switch SW3 from an off state to an on state.Accordingly, the supply voltage based on the USB power delivery from thesupply terminal T2 for the second input voltage 2 is used for thecharging of the secondary battery 26 through the step-down DC-DCconverter 2121, the switch SW2 and the P channel MOS transistor Mp0 andused for the supply of power to the power receiving side system 3.

On the other hand, when non-switching indication information indicativeof non-switching from the wireless power delivery to the USB powerdelivery is outputted at Step S807, the process for the automaticselecting operation is returned to Step S509, where the gate drivecircuit 21249 maintains the first gate drive output signal Mp1_G and thesecond gate drive output signal Mp2_G at low and high levelsrespectively. Accordingly, since the P channel MOS transistor Mp1 and Pchannel MOS transistor Mp2 of the input voltage selection switch 21242are respectively maintained in an on state and an off state, the initialoperation of the wireless power delivery is maintained. Further, at thisStep S509, the control logic circuit 21245 maintains the switch SW2lying inside the semiconductor integrated circuit 212 according to thethird embodiment shown in FIG. 2 in an on state and on the other hand,holds the switch SW3 in an off state. Accordingly, the supply voltagebased on the wireless power delivery from the supply terminal T1 for thefirst input voltage 1 is used for the charging of the secondary battery26 through the step-down DC-DC converter 2121, the switch SW2 and the Pchannel MOS transistor Mp0 and used for the supply of power to the powerreceiving side system 3.

Although the invention made above by the present inventors has beendescribed specifically on the basis of various embodiments, the presentinvention is not limited to the embodiments referred to above. It isneedless to say that various changes can be made thereto within thescope not departing from the gist thereof.

For example, electronic devices each equipped with the presentsemiconductor integrated circuit are not limited to portable personalcomputers like a multifunction cellular phone, a tablet PC and the like,but can be applied to a digital video camera, a digital still camera, aportable music player, a portable DVD player, etc.

Further, the electronic devices each equipped with the presentsemiconductor integrated circuit are applicable to cellular phoneshaving functions of an automatic ticket system, e-cash and the like inhaving an RFID card built-in.

1-21. (canceled)
 22. A semiconductor integrated circuit comprising: afirst supply terminal capable of supplying a first power supply voltage;a second supply terminal capable of supplying a second power supplyvoltage; an input voltage selection circuit coupled to the first supplyterminal and the second supply terminal; a first power supply switch;and a second power supply switch, wherein the input voltage selectioncircuit includes a power-on reset circuit, an input voltage detectioncircuit and a control circuit, wherein in response to the supply of thefirst power supply voltage to the first supply terminal and the supplyof the second power supply voltage to the second supply terminal, thepower-on reset circuit generates a power on reset signal, wherein theinput voltage detection circuit generates a first voltage detectionoutput signal in response to the supply of the first power supplyvoltage to the first supply terminal and generates a second voltagedetection output signal in response to the supply of the second powersupply voltage to the second supply terminal, wherein the controlcircuit controls the first power supply switch and the second powersupply switch in response to the power on reset signal, the firstvoltage detection output signal and the second voltage detection outputsignal, wherein the input voltage detection circuit detects the supplyof the first power supply voltage to the first supply terminal and thesupply of the second power supply voltage to the second supply terminalat a timing of a change in the level of the power on reset signalresponsive to an end of a power on reset operation of the power-on resetcircuit, wherein in a case where, at the timing of the change in thelevel of the power on reset signal, the input voltage detection circuitdetects the supply of the first power supply voltage to the first supplyterminal and the supply of the second power supply voltage to the secondsupply terminal, the control circuit controls one of the first powersupply switch and the second power supply switch and the other thereofto an on state and an off state respectively after the end of the poweron reset operation, wherein in said case, the one of the first powersupply switch and the second power supply switch and the other thereofare respectively controlled to the on state and the off state inaccordance with an order of precedence set to the control circuit inadvance, and wherein the one thereof controlled to the on state suppliesthe first power supply voltage or the second power supply voltagesupplied to the first supply terminal or the second supply terminal tothe load.
 23. The semiconductor integrated circuit according to claim22, further comprising: a first external output terminal and a secondexternal output terminal which supply the first power supply voltage orthe second power supply voltage to a first external load and a secondexternal load taken as the load respectively; and an output P channelMOS transistor coupled between the first external output terminal andthe second external output terminal, wherein when either of the firstpower supply switch and the second power supply switch is controlled toan on state after the end of the power on reset operation, the output Pchannel MOS transistor is controlled to an on state by the controlcircuit, and wherein the control of the output P channel MOS transistorto the on state enables the first power supply voltage or the secondpower supply voltage to be supplied to the second external load throughthe output P channel MOS transistor and the second external outputterminal.
 24. The semiconductor integrated circuit according to claim23, wherein the first external output terminal is configured to supplythe first power supply voltage or the second power supply voltage to thefirst external load corresponding to another semiconductor integratedcircuit taken as an active device, and wherein the output P channel MOStransistor and the second external output terminal are configured tosupply the first power supply voltage or the second power supply voltageto the second external load taken as a battery.
 25. The semiconductorintegrated circuit according to claim 24, wherein the input voltageselection circuit further comprises: an input voltage selection switch;and a gate drive circuit, wherein the input voltage selection switchincludes a first input P channel MOS transistor and a second input Pchannel MOS transistor, the first input P channel MOS transistor havinga source coupled to the first supply terminal and the second input Pchannel MOS transistor having a source coupled to the second supplyterminal, wherein during a power on reset period of the power-on resetcircuit, the gate drive circuit controls both of the first and secondinput P channel MOS transistors of the input voltage selection switch toan on state, and wherein during the power on reset period, an operatingvoltage to be supplied to the power-on reset circuit is generated from adrain of the first input P channel MOS transistor or a drain of thesecond input P channel MOS transistor.
 26. The semiconductor integratedcircuit according to claim 25, wherein, in said case, the gate drivecircuit controls one of the first and second input P channel MOStransistors of the input voltage selection switch and the other thereofto an on state and an off state respectively in accordance with theorder of precedence set to the control circuit in advance.
 27. Thesemiconductor integrated circuit according to claim 26, wherein theinput voltage selection circuit further comprises: a voltagecomparison/selection circuit having a first input terminal, a secondinput terminal and an output terminal, wherein the first input terminalof the voltage comparison/selection circuit is coupled to the drain ofthe first input P channel MOS transistor of the input voltage selectionswitch, wherein the second input terminal of the voltagecomparison/selection circuit is coupled to the drain of the second inputP channel MOS transistor of the input voltage selection switch, whereinthe operating voltage supplied to the power-on reset circuit isgenerated from the output terminal of the voltage comparison/selectioncircuit, and wherein the voltage comparison/selection circuit compares avoltage of the first input terminal and a voltage of the second inputterminal to select a high voltage and thereby outputs the high voltageas the operating voltage supplied from the output terminal to thepower-on reset circuit.
 28. The semiconductor integrated circuitaccording to claim 24, further comprising: a step-down DC-DC converterand a linear regulator coupled in parallel between the first supplyterminal and the first power supply switch, wherein the linear regulatoroperates as a series regulator which quickly operates immediately afterpower-on based on the supply of the first power supply voltage to thefirst supply terminal, and wherein the step-down DC-DC converteroperates as a switching regulator having power efficiency higher thanthe linear regulator.
 29. The semiconductor integrated circuit accordingto claim 28, wherein the first supply terminal is configured to supply apower supply voltage based on a wireless power delivery to the firstsupply terminal through a first Schottky diode and an AC-DC conversionpower supply voltage of an AC power supply coupling interface theretothrough a second Schottky diode, and wherein the second supply terminalis configured to supply a USB power supply voltage of a USB couplinginterface to the second supply terminal.